1. Technical Field
This disclosure relates to semiconductor memory fabrication and more particularly, to a method for fabricating enlarged stacked capacitors by employing isotropic etching.
2. Description of the Related Art
Semiconductor memory cells include capacitors accessed by transistors to store data. Data is stored as a high or low bit depending on the state of the capacitor cell. The capacitor's charge or lack of charge indicates a high or low when accessed to read data, and the capacitor is charged or discharged to write data from the capacitor through a bit-line sense amplifier circuit.
Stacked capacitors are among the types of capacitors used in semiconductor memories, for example, dynamic random access memories (DRAM). Stacked capacitors are typically located on top of the cell transistor used to access a storage node of the capacitor as opposed to trench capacitors which are buried in the substrate of the device. Higher cell capacitance is beneficial for improving data sensing margin in DRAM devices.
In semiconductor memories, such as dynamic random access memories (DRAM) which include stacked capacitors, an area for a memory cell is proportional to the size of a stacked capacitor. For sub-8F.sup.2 stacked capacitor DRAMs, i.e., DRAMs with memory cells occupying an area of less than 8F.sup.2 where F is a minium feature size of a given technology, the projected area of capacitor is drastically decreased. For example, only 1F.sup.2 of area for a 4F.sup.2 cell is available for the stacked capacitor and only 2F.sup.2 of area for a 6F.sup.2 cell is available for the stacked capacitor, while 3F.sup.2 of area is available for the stacked capacitor in a 8F.sup.2 cell. Thus, cell capacitance is also drastically decreased with the decrease minimum feature size (F) and also the decrease of cells in a layout.
Referring to FIG. 1, a layout for 8F.sup.2 memory cells each having a stacked capacitor is shown. In the layout, stacked capacitors 10 are disposed in rows and columns. Active areas 12 are shown between pairs of stacked capacitors 10. Active areas 12 are surrounded by shallow trench isolation regions 14.
Referring to FIG. 2, a cross-sectional view is shown taken at section line 2--2 of FIG. 1. FIG. 2 illustratively depicts the major elements of the 8F.sup.2 memory cells. Stacked capacitors 10 are shown having a top electrode 16, a bottom electrode 18 and a capacitor dielectric layer 20 therebetween. Bottom electrode 18 is connected to a plug 22 which extends down to a portion of active area 12. Active areas 12 form an access transistor for charging and discharging stacked capacitor 10 in accordance with data on a bitline 24. Bitline 24 is coupled to a portion of active area 12 (source or drain of the access transistor) by a contact 23. When a gate conductor 28 is activated the access transistor conducts and charges or discharges stacked capacitor 10. When F is reduced with each new generation of DRAM design, stacked capacitor 12 loses area thereby reducing the capacitors capabilities. A typical capacitor area for an 8F.sup.2 memory cell is equal to about 3F.sup.2.
Referring to FIG. 3, a layout for 6F.sup.2 memory cells each having a stacked capacitor is shown. In the layout, stacked capacitors 30 are disposed in rows and columns. Active areas 32 are shown between pairs of stacked capacitors 30, similar to FIG. 1. Active areas 32 are surrounded by narrower shallow trench isolation regions 34.
Referring to FIG. 4, a cross-sectional view is shown taken at section line 4--4 of FIG. 3. FIG. 4 illustratively depicts the major elements of the 6F.sup.2 memory cells. Stacked capacitors 30 are shown having a top electrode 36, a bottom electrode 38 and a capacitor dielectric layer 40 therebetween. Bottom electrode 38 is connected to a plug 42 which extends down to a portion of active area 32. Active areas 32 form an access transistor for charging and discharging stacked capacitor 30 in accordance with data on a bitline 44. Bitline 44 is coupled to a portion of active area 32 (source or drain of the access transistor) by a contact 43. When a gate conductor 48 is activated the access transistor conducts and charges or discharges stacked capacitor 30. Stacked capacitors 30 are smaller than those of the 8F.sup.2 memory cells. When F is reduced with each new generation of DRAM design, stacked capacitor 30 losses area thereby reducing the capacitors capabilities. A typical capacitor area for a 6F.sup.2 memory cell is equal to about 2F.sup.2.
Therefore, a need exists for a method for increasing or maintaining stacked capacitor area while reducing the size of memory cells.